发明申请
US20080072184A1 Method of Achieving Timing Closure in Digital Integrated Circuits by Optimizing Individual Macros
失效
通过优化单个宏来实现数字集成电路中的定时闭合的方法
- 专利标题: Method of Achieving Timing Closure in Digital Integrated Circuits by Optimizing Individual Macros
- 专利标题(中): 通过优化单个宏来实现数字集成电路中的定时闭合的方法
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申请号: US11942034申请日: 2007-11-19
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公开(公告)号: US20080072184A1公开(公告)日: 2008-03-20
- 发明人: Jun Zhou , David Hathaway , Chandramouli Visweswariah , Patrick Williams
- 申请人: Jun Zhou , David Hathaway , Chandramouli Visweswariah , Patrick Williams
- 申请人地址: US NY ARMONK
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY ARMONK
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.
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