发明申请
- 专利标题: Re-Quantization in downlink receiver bit rate processor
- 专利标题(中): 下行接收器比特率处理器中的重量化
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申请号: US11529071申请日: 2006-09-28
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公开(公告)号: US20080081575A1公开(公告)日: 2008-04-03
- 发明人: Deepak Mathew , Aiguo Yan , Krishnan Vishwanathan , Eric Aardoom , Timothy Fisher-Jeffes
- 申请人: Deepak Mathew , Aiguo Yan , Krishnan Vishwanathan , Eric Aardoom , Timothy Fisher-Jeffes
- 申请人地址: US MA Norwood
- 专利权人: Analog Devices, Inc.
- 当前专利权人: Analog Devices, Inc.
- 当前专利权人地址: US MA Norwood
- 主分类号: H04B1/18
- IPC分类号: H04B1/18
摘要:
A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.
公开/授权文献
- US08358987B2 Re-quantization in downlink receiver bit rate processor 公开/授权日:2013-01-22