Invention Application
US20080091998A1 Partial Enhanced Scan Method for Reducing Volume of Delay Test Patterns
审中-公开
用于减少延迟测试模式的体积的部分增强扫描方法
- Patent Title: Partial Enhanced Scan Method for Reducing Volume of Delay Test Patterns
- Patent Title (中): 用于减少延迟测试模式的体积的部分增强扫描方法
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Application No.: US11851137Application Date: 2007-09-06
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Publication No.: US20080091998A1Publication Date: 2008-04-17
- Inventor: Seongmoon Wang
- Applicant: Seongmoon Wang
- Applicant Address: US NJ Princeton
- Assignee: NEC LABORATORIES AMERICA, INC.
- Current Assignee: NEC LABORATORIES AMERICA, INC.
- Current Assignee Address: US NJ Princeton
- Main IPC: G01R31/3183
- IPC: G01R31/3183

Abstract:
A method includes selecting at least one regular scan cell that is replaced with a corresponding one of an enhanced scan cell in a scan chain for scan based delay testing of the digital circuit, controlling the enhanced scan cell with a skewed load approach, and controlling regular scan cells of the scan chain with a broadside approach. More specifically, this reduces test sequence lengths and achieves higher delay fault coverage, without having to pay high cost to drive all scan cells by the skewed load approach, which requires a faster switching than the broadside approach. No additional pins are required for driving enhanced scan cells because the drive signal for switching the enhanced scan cells is derived from the signal for driving the regular scan cells.
Information query
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