发明申请
US20080094929A1 TWO-CYCLE SENSING IN A TWO-TERMINAL MEMORY ARRAY HAVING LEAKAGE CURRENT
有权
具有漏电流的两端存储器阵列中的双周期感测
- 专利标题: TWO-CYCLE SENSING IN A TWO-TERMINAL MEMORY ARRAY HAVING LEAKAGE CURRENT
- 专利标题(中): 具有漏电流的两端存储器阵列中的双周期感测
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申请号: US11583676申请日: 2006-10-19
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公开(公告)号: US20080094929A1公开(公告)日: 2008-04-24
- 发明人: Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
- 申请人: Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
- 主分类号: G11C11/00
- IPC分类号: G11C11/00 ; G11C7/02
摘要:
A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.
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