Invention Application
US20080099874A1 SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF REALIZING REDUCTION IN SIZE
审中-公开
具有实现减小尺寸的半导体集成电路
- Patent Title: SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF REALIZING REDUCTION IN SIZE
- Patent Title (中): 具有实现减小尺寸的半导体集成电路
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Application No.: US11923132Application Date: 2007-10-24
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Publication No.: US20080099874A1Publication Date: 2008-05-01
- Inventor: Hiroshi Kumano
- Applicant: Hiroshi Kumano
- Applicant Address: JP Kyoto
- Assignee: ROHM CO., LTD.
- Current Assignee: ROHM CO., LTD.
- Current Assignee Address: JP Kyoto
- Priority: JP2006-292089 20061027
- Main IPC: H01L29/00
- IPC: H01L29/00

Abstract:
In a semiconductor integrated circuit in which an element isolating insulation film is provided on a substrate, an isolated Si region in the substrate is a shape composed of straight lines which form four sides and circular arcs which form four corners. Further, the adjacent Si regions share element isolating insulation films, and the adjacent Si regions are separated by one element isolating insulation film. Furthermore, widths of the element isolating insulation films are the same in a chip pattern. When the width of the element isolating insulation film is set to a, and a curvature radius of curved lines at four corners of the Si region is set to r; the width a and the curvature radius r are determined so as to satisfy conditions of r>0.7a in the case where the element isolating insulation films are intersected only in a cross shape, and r>1.5a in the case where the element isolating insulation films include a portion intersected in a T shape.
Information query
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