发明申请
- 专利标题: Biasing circuit for EEPROM memories with shared latches
- 专利标题(中): 具有共享锁存器的EEPROM存储器的偏置电路
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申请号: US11977876申请日: 2007-10-26
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公开(公告)号: US20080101125A1公开(公告)日: 2008-05-01
- 发明人: Antonino Conte , Gianbattista Logiudice , Giovanni Matranga , Mario Micciche' , Carmelo Ucciardello , Diego De Costantini
- 申请人: Antonino Conte , Gianbattista Logiudice , Giovanni Matranga , Mario Micciche' , Carmelo Ucciardello , Diego De Costantini
- 申请人地址: IT Agrate Brianza
- 专利权人: STMicroelectronics S.R.L.
- 当前专利权人: STMicroelectronics S.R.L.
- 当前专利权人地址: IT Agrate Brianza
- 优先权: ITMI2006A002068 20061027
- 主分类号: G11C16/04
- IPC分类号: G11C16/04
摘要:
An EEPROM memory having a matrix of individually selectable memory cells, the matrix having a plurality of columns, a plurality of data lines each coupled with the cells of a corresponding column, the data lines being grouped in a plurality of packets, a plurality of biasing elements for providing a biasing signal to the data lines, and means for selecting the biasing elements for a selected one of the packets, wherein each biasing element is associated with corresponding data lines of a plurality of packets, the biasing element comprising switching means for selectively applying the biasing signal to a selected one of the associated data lines.
公开/授权文献
- US07742342B2 Biasing circuit for EEPROM memories with shared latches 公开/授权日:2010-06-22
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