发明申请
- 专利标题： Parallel LDPC Decoder
- 专利标题（中）： 并行LDPC解码器
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申请号： US11565670申请日： 2006-12-01
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公开(公告)号： US20080134008A1公开(公告)日： 2008-06-05
- 发明人: Alexander Andreev , Igor Vikhliantsev , Sergey Gribok
- 申请人： Alexander Andreev , Igor Vikhliantsev , Sergey Gribok
- 申请人地址： US CA Milpitas
- 专利权人： LSI LOGIC CORPORATION
- 当前专利权人： LSI LOGIC CORPORATION
- 当前专利权人地址： US CA Milpitas
- 主分类号： H03M13/07
- IPC分类号： H03M13/07 ; G06F11/10
摘要：
An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations.
公开/授权文献
- US07934139B2 Parallel LDPC decoder 公开/授权日：2011-04-26
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