发明申请
US20080136498A1 Method and System for Buffering A Clock Signal 审中-公开
缓冲时钟信号的方法和系统

Method and System for Buffering A Clock Signal
摘要:
A method and system for buffering a clock signal is provided. The method may include self-biasing a PMOS transistor of a buffer, utilized for amplifying an in-phase/quadrature phase signal, to produce a first bias voltage at the gate of a PMOS transistor, and biasing an NMOS transistor of the buffer via a controllable current source to produce a second bias voltage at the gate of the NMOS transistor. The gain of the buffer may be controlled by varying a controllable current source coupled to a second NMOS transistor configured as a diode. Two coupling capacitors may be utilized to remove a DC component of the signal. Multiple buffers may be coupled end-to-end to increase the overall drive capability, where the channel width of the transistors within the transistors may be doubled in each successive buffer.
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