发明申请
US20080144396A1 ERASING FLASH MEMORY USING ADAPTIVE DRAIN AND/OR GATE BIAS 有权
使用自适应排水和/或门偏差擦除闪存

  • 专利标题: ERASING FLASH MEMORY USING ADAPTIVE DRAIN AND/OR GATE BIAS
  • 专利标题(中): 使用自适应排水和/或门偏差擦除闪存
  • 申请号: US11612863
    申请日: 2006-12-19
  • 公开(公告)号: US20080144396A1
    公开(公告)日: 2008-06-19
  • 发明人: Kuo-Tung ChangWei Zheng
  • 申请人: Kuo-Tung ChangWei Zheng
  • 主分类号: G11C16/16
  • IPC分类号: G11C16/16
ERASING FLASH MEMORY USING ADAPTIVE DRAIN AND/OR GATE BIAS
摘要:
A hot hole erase operation as described herein can be utilized for a flash memory device having an array of memory cells. The erase operation employs an adaptive erase bias voltage scheme where the drain bias voltage (and/or the gate bias voltage) is dynamically adjusted in response to an erase pulse count corresponding to a preliminary erase operation during which a relatively small portion of a sector is erased. The adjustment of the erase bias voltage in this manner enables the rest of the sector to be erased using erase bias voltages that are better suited to the current erase characteristics of the sector.
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