发明申请
US20080148025A1 High performance raid-6 system architecture with pattern matching 有权
具有模式匹配的高性能raid-6系统架构

High performance raid-6 system architecture with pattern matching
摘要:
An acceleration unit offloads computationally intensive tasks from a processor. The acceleration unit includes two data processing paths each having an Arithmetic Logical Unit and sharing a single multiplier unit. Each data processing path may perform configurable operations in parallel on a same data. Special multiplexer paths and instructions are provided to allow P and Q type syndromes to be computed on a stripe in a single-pass of the data through the acceleration unit.
信息查询
0/0