发明申请
- 专利标题: Transmitting and receiving circuit and semiconductor device including the same
- 专利标题(中): 发射和接收电路和包括其的半导体器件
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申请号: US12003112申请日: 2007-12-20
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公开(公告)号: US20080149738A1公开(公告)日: 2008-06-26
- 发明人: Masashi Fujita , Yutaka Shionoiri
- 申请人: Masashi Fujita , Yutaka Shionoiri
- 申请人地址: JP Atsugi-shi
- 专利权人: Semiconductor Energy Laboratory Co., Ltd.
- 当前专利权人: Semiconductor Energy Laboratory Co., Ltd.
- 当前专利权人地址: JP Atsugi-shi
- 优先权: JP2006-349945 20061226
- 主分类号: G06K19/06
- IPC分类号: G06K19/06
摘要:
An object is to provide a circuit configuration with which the number of transistors can be reduced and power conversion efficiency can be prevented from being reduced, in a transmitting and receiving circuit. The transmitting and receiving circuit includes a voltage doubler rectifier circuit having N stages, each of which includes a capacitor, where N is a positive integer. The voltage doubler rectifier circuit having N stages is connected to a circuit having a modulation function. In the capacitor in any one of the N stages, one electrode of the one capacitor is connected to an input terminal of the transmitting and receiving circuit, and a node to which the other electrode of the one capacitor is connected is connected to a circuit having a demodulation function. Since the transmitting and receiving circuit can be formed of fewer transistors, it can be reduced in size. Since a reduction in power conversion efficiency can be prevented, a power supply potential can be efficiently generated.
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