发明申请
US20080150610A1 System and method for compensating for PVT variation effects on the delay line of a clock signal
失效
用于补偿PVT变化对时钟信号的延迟线的影响的系统和方法
- 专利标题: System and method for compensating for PVT variation effects on the delay line of a clock signal
- 专利标题(中): 用于补偿PVT变化对时钟信号的延迟线的影响的系统和方法
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申请号: US11643492申请日: 2006-12-21
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公开(公告)号: US20080150610A1公开(公告)日: 2008-06-26
- 发明人: Terence Magee , Thomas Hughes , Cheng- Gang Kong
- 申请人: Terence Magee , Thomas Hughes , Cheng- Gang Kong
- 主分类号: H01L35/00
- IPC分类号: H01L35/00
摘要:
The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online/offline swapping of data paths requiring a dedicated FIFO (First-in First-out) buffer design. Delay cells are trained for each clock path (namely a Functional delay) and a spare delay cell is trained. A ratio is calculated for each Functional delay cell by dividing the Functional delay cells' setting into the spare delay cells' one-fourth cycle setting. These ratios reflect any process variation. Functional mode is then entered and a Master-Slave approach switched to, during which the spare delay cell repeats the training sequence continuously while the Functional delay cells delay the clocks from the RAM (Random Access Memory). Each Functional delay cell is updated at the end of each training sequence of the spare delay cell, compensating for voltage and temperature change, by dividing the ratio into the new spare delay cell one-fourth cycle setting.