发明申请
US20080159377A1 HIGH PERFORMANCE EQUALIZER WITH ENHANCED DFE HAVING REDUCED COMPLEXITY
审中-公开
高性能均衡器与增强的DFE具有降低的复杂性
- 专利标题: HIGH PERFORMANCE EQUALIZER WITH ENHANCED DFE HAVING REDUCED COMPLEXITY
- 专利标题(中): 高性能均衡器与增强的DFE具有降低的复杂性
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申请号: US12043517申请日: 2008-03-06
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公开(公告)号: US20080159377A1公开(公告)日: 2008-07-03
- 发明人: Steve A. Allpress , Quinn Li
- 申请人: Steve A. Allpress , Quinn Li
- 主分类号: G06F17/10
- IPC分类号: G06F17/10 ; H03H7/30
摘要:
An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) (2) performs equalization in a time-forward or time-reversed manner based on the channel being minimum-phase or maximum-phase to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1
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