发明申请
- 专利标题： Cache Memory and Control Method Thereof
- 专利标题（中）： 缓存内存及其控制方法
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申请号： US10577133申请日： 2004-11-02
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公开(公告)号： US20080168232A1公开(公告)日： 2008-07-10
- 发明人: Hazuki Okabayashi , Ryuta Nakanishi , Tetsuya Tanaka , Shuji Miyasaka
- 申请人： Hazuki Okabayashi , Ryuta Nakanishi , Tetsuya Tanaka , Shuji Miyasaka
- 优先权： JP2003-387351 20031118
- 国际申请： PCT/JP04/16272 WO 20041102
- 主分类号： G06F12/00
- IPC分类号： G06F12/00
摘要：
A cache memory according to the present invention includes: a W flag setting unit (40) that modifies order data indicating an access order per cache entry that holds a data unit of a cache so as to reflect an actual access order; and a replace unit (39) that selects a cache entry for replacement based on the modified order data and replaces the cache entry.
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