A design structure for implementing redundancy programming in a memory macro of an integrated circuit chip. It is assumed that all fails are row fails until determined to be bitline fails, circuit means for implementing a method wherein it is assumed that all fails are row fails until determined to be bitline fails and test patterns are passed back to the failure detecting circuit when a wordline destination of the test patterns has previously been determined to be failing, and the test patterns and resultant patterns are passed between the memory macro and a test engine via logic paths connecting the memory macro to other circuits in said integrated circuit chip.