发明申请
US20080192877A1 PHASE ALIGNMENT MECHANISM FOR MINIMIZING THE IMPACT OF INTEGER-CHANNEL INTERFERENCE IN A PHASE LOCKED LOOP
审中-公开
用于最小化相位锁定环路中整数通道干扰的影响的相位对准机制
- 专利标题: PHASE ALIGNMENT MECHANISM FOR MINIMIZING THE IMPACT OF INTEGER-CHANNEL INTERFERENCE IN A PHASE LOCKED LOOP
- 专利标题(中): 用于最小化相位锁定环路中整数通道干扰的影响的相位对准机制
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申请号: US12029456申请日: 2008-02-11
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公开(公告)号: US20080192877A1公开(公告)日: 2008-08-14
- 发明人: Oren E. Eliezer , Manouchehr Entezari , Robert B. Staszewski , Sumeer Bhatara
- 申请人: Oren E. Eliezer , Manouchehr Entezari , Robert B. Staszewski , Sumeer Bhatara
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 主分类号: H04L7/00
- IPC分类号: H04L7/00
摘要:
A novel and useful apparatus for and method of minimizing the impact of interference on the phase error performance in a phase locked loop (PLL) at integer channels by adjustment of the phase of the interfering signal such that its impact on the reference signal is minimized. Phase control is achieved by use of the digital architecture of the ADPLL and its insensitivity to an arbitrary phase bias introduced between its digitally represented output and reference phase signals. The optimal phase relationship for each integer channel is determined through a calibration procedure in which the phase is swept and the optimal phase is recorded. Before the transmission of a payload on an integer channel, the phase relationship between the output RF signal and the input reference signal is adjusted to the value found to be optimal for that frequency, based on the values previously recorded during the calibration procedure.
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