发明申请
- 专利标题: METHOD AND APPARATUS FOR MEASURING PIPELINE STALLS IN A MICROPROCESSOR
- 专利标题(中): 用于测量微处理器中管道的方法和装置
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申请号: US11675112申请日: 2007-02-15
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公开(公告)号: US20080201566A1公开(公告)日: 2008-08-21
- 发明人: Venkat Rajeev Indukuru , Alexander Erik Mericas
- 申请人: Venkat Rajeev Indukuru , Alexander Erik Mericas
- 主分类号: G06F9/38
- IPC分类号: G06F9/38
摘要:
A computer implemented method, apparatus, and computer program product for monitoring execution of instructions in an instruction pipeline. The process identifies a number of stall cycles for a group of instructions to complete execution. The process retrieves a deterministic latency pattern corresponding to the group of instructions. The process compares the number of stall cycles to the deterministic execution latency pattern. The process identifies the instruction as a dependent instruction in response to a determination that an instruction in the group of instructions completed a deterministic number of cycles after an antecedent instruction completed.
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