发明申请
- 专利标题: Method and System for Testing an Integrated Circuit
- 专利标题(中): 集成电路测试方法和系统
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申请号: US12022422申请日: 2008-01-30
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公开(公告)号: US20080205173A1公开(公告)日: 2008-08-28
- 发明人: Joerg Kliewer , Klaus Nierle , Martin Versen
- 申请人: Joerg Kliewer , Klaus Nierle , Martin Versen
- 优先权: DE102007004555.9 20070130
- 主分类号: G01R31/02
- IPC分类号: G01R31/02 ; G01R31/3187 ; G11C29/00
摘要:
An integrated circuit comprising: a) at least one integrated voltage generator for generating a low voltage for an associated integrated load; b) an integrated voltage generator test logic connected to the voltage generator which in a test operating mode which is the operating state of that integrated voltage generator between an active operating state and a standby operating state depending on an external control signal; c) an internal load switch for switching said generated load voltage to that integrated load said internal load switch being controllable by means of an internal control signal; d) wherein said voltage generator test logic in said test operating mode switches the operating state of said integrated voltage generator independently of the associated internal control switching signal for setting a temporal voltage profile of said load voltage applied to that load.
公开/授权文献
- US07729186B2 Method and system for testing an integrated circuit 公开/授权日:2010-06-01
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