发明申请
- 专利标题: Semiconductor device having a triple gate transistor and method for manufacturing the same
- 专利标题(中): 具有三栅极晶体管的半导体器件及其制造方法
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申请号: US12008232申请日: 2008-01-09
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公开(公告)号: US20080211022A1公开(公告)日: 2008-09-04
- 发明人: Shigenobu Maeda , Jeong Hwan Yang , Junga Choi
- 申请人: Shigenobu Maeda , Jeong Hwan Yang , Junga Choi
- 申请人地址: KR Suwon-si
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR Suwon-si
- 优先权: KR04-11328 20040220
- 主分类号: H01L29/00
- IPC分类号: H01L29/00 ; H01L21/336
摘要:
In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction. A multi-gate transistor is formed on the SOI layer. The first direction and the second direction are the same, or the first direction is at 45 degrees with respect to the second direction. In another aspect of the invention, the intersection of the top and side surfaces of the active region are curved, further reducing NBTI. In another aspect of the invention, a multi-gate transistor is formed on a shallow trench isolation region of a bulk wafer.
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