发明申请
US20080217782A1 METHOD FOR PREPARING 2-DIMENSIONAL SEMICONDUCTOR DEVICES FOR INTEGRATION IN A THIRD DIMENSION 有权
制备用于集成在第三维中的二维半导体器件的方法

METHOD FOR PREPARING 2-DIMENSIONAL SEMICONDUCTOR DEVICES FOR INTEGRATION IN A THIRD DIMENSION
摘要:
A method which is intended to facilitate and/or simplify the process of fabricating interlayer vias by selective modification of the FEOL film stack on a transfer wafer is provided. Specifically, the present invention provides a method in which two dimensional devices are prepared for subsequent integration in a third dimension at the transition between normal FEOL processes by using an existing interlayer contact mask to define regions in which layers of undesirable dielectrics and metal are selectively removed and refilled with a middle-of-the-line (MOL) compatible dielectric film. As presented, the inventive method is compatible with standard FEOL/MOL integration schemes, and it guarantees a homogeneous dielectric film stack specifically in areas where interlayer contacts are to be formed, thus allowing the option of a straightforward integration path, if desired.
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