发明申请
- 专利标题: INTERNAL CLOCK GENERATOR, SYSTEM AND METHOD
- 专利标题(中): 内部时钟发生器,系统和方法
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申请号: US12045125申请日: 2008-03-10
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公开(公告)号: US20080224752A1公开(公告)日: 2008-09-18
- 发明人: Chul-Ho LEE , Jin-Yub LEE
- 申请人: Chul-Ho LEE , Jin-Yub LEE
- 申请人地址: KR Suwon-si
- 专利权人: SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人: SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人地址: KR Suwon-si
- 优先权: KR10-2007-0025197 20070314
- 主分类号: G06F1/04
- IPC分类号: G06F1/04
摘要:
An internal clock generator, system and method of generating the internal clock are disclosed. The method comprises detecting the level of an operating voltage within the system, comparing the level of the operating voltage to a target voltage level and generating a corresponding detection signal, and selecting between a normal clock and an alternate clock having a period longer than the period of the normal clock in relation to the detection signal and generating an internal clock on the basis of the selection.
公开/授权文献
- US07772910B2 Internal clock generator, system and method 公开/授权日:2010-08-10
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