发明申请
US20080230912A1 WAFER-LEVEL STACK PACKAGE AND METHOD OF FABRICATING THE SAME
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WAFER LEVEL STACK PACKAGE AND METHOD OF FABRICATING THE SAME
- 专利标题： WAFER-LEVEL STACK PACKAGE AND METHOD OF FABRICATING THE SAME
- 专利标题（中）： WAFER LEVEL STACK PACKAGE AND METHOD OF FABRICATING THE SAME
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申请号： US12053478申请日： 2008-03-21
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公开(公告)号： US20080230912A1公开(公告)日： 2008-09-25
- 发明人: In-Young Lee , Ho-Jin Lee , Hyun-Soo Chung , Ju-Il Choi , Son-Kwan Hwang
- 申请人： In-Young Lee , Ho-Jin Lee , Hyun-Soo Chung , Ju-Il Choi , Son-Kwan Hwang
- 申请人地址： KR Gyeonggi-do
- 专利权人： SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人： SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人地址： KR Gyeonggi-do
- 优先权： KR2007-0028864 20070323
- 主分类号： H01L23/48
- IPC分类号： H01L23/48 ; H01L21/4763
摘要：
A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.
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