Invention Application
US20080242000A1 WAFER-LEVEL-CHIP-SCALE PACKAGE AND METHOD OF FABRICATION
有权
WAFER-LEVEL-CHIP-SCALE包装和制造方法
- Patent Title: WAFER-LEVEL-CHIP-SCALE PACKAGE AND METHOD OF FABRICATION
- Patent Title (中): WAFER-LEVEL-CHIP-SCALE包装和制造方法
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Application No.: US12139771Application Date: 2008-06-16
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Publication No.: US20080242000A1Publication Date: 2008-10-02
- Inventor: Yong-hwan KWON , Chung-sun LEE , Woon-byung KANG
- Applicant: Yong-hwan KWON , Chung-sun LEE , Woon-byung KANG
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Priority: KR10-2005-0066960 20050722
- Main IPC: H01L21/00
- IPC: H01L21/00
Abstract:
A wafer-level-chip-scale package and related method of fabrication are disclosed. The wafer-level-chip-scale package comprises a semiconductor substrate comprising an integrated circuit, a conductive ball disposed on the semiconductor substrate and electrically connected to the integrated circuit, and a protective portion formed from an insulating material and disposed on bottom and side surfaces of the semiconductor substrate.
Public/Granted literature
- US07569423B2 Wafer-level-chip-scale package and method of fabrication Public/Granted day:2009-08-04
Information query
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