发明申请
US20080244187A1 PIPELINING D STATES FOR MRU STEERAGE DURING MRU-LRU MEMBER ALLOCATION 有权
在MRU-LRU会员分配期间管理MRU的管理状态

PIPELINING D STATES FOR MRU STEERAGE DURING MRU-LRU MEMBER ALLOCATION
摘要:
A method and apparatus for preventing selection of Deleted (D) members as an LRU victim during LRU victim selection. During each cache access targeting the particular congruence class, the deleted cache line is identified from information in the cache directory. A location of a deleted cache line is pipelined through the cache architecture during LRU victim selection. The information is latched and then passed to MRU vector generation logic. An MRU vector is generated and passed to the MRU update logic, which is selects/tags the deleted member as a MRU member. The make MRU operation affects only the lower level LRU state bits arranged in a tree-based structure state bits so that the make MRU operation only negates selection of the specific member in the D state, without affecting LRU victim selection of the other members.
信息查询
0/0