A method of designing a three-dimensional integrated circuit includes dividing two-dimensional layout data of a circuit formed on a semiconductor substrate into a plurality of layout block data in order to re-arrange in different layers, generating layout block data reversing one of the layout block data of two folded layers arranged vertically adjacent to each other, alternately arranging the reversed layout block data and non-reverse block layout data to form a plurality of layers vertically overlapped, selecting at least one from interconnects included in a plurality of layout block data of the circuit and ranging over plural layers so as to be mutually and functionally collected together with respect to at least one of time delay, interconnect length and block configuration, and re-arranging the selected interconnect using a via connecting an upper layer and an under layer of the folded interconnect.