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发明申请
US20080246752A1 Display, Timing Controller and Column Driver Integrated Circuit Using Clock Embedded Multi-Level Signaling 有权
显示，定时控制器和列驱动器集成电路使用时钟嵌入式多级信号

  • 专利标题： Display, Timing Controller and Column Driver Integrated Circuit Using Clock Embedded Multi-Level Signaling
  • 专利标题（中）： 显示，定时控制器和列驱动器集成电路使用时钟嵌入式多级信号
  • 申请号： US12066553
    申请日： 2005-11-10
  • 公开(公告)号： US20080246752A1
    公开(公告)日： 2008-10-09
  • 发明人: Yong-Jae Lee
  • 申请人： Yong-Jae Lee
  • 优先权： KR10-2005-0088619 20050923
  • 国际申请： PCT/KR05/03678 WO 20051110
  • 主分类号： G09G5/00
  • IPC分类号： G09G5/00
Display, Timing Controller and Column Driver Integrated Circuit Using Clock Embedded Multi-Level Signaling
摘要：
The present invention relates to a display, a timing controller and a column driver IC, and more particularly to a display, timing controller and column driver integrated circuit using clock embedded multi-level signaling. The present invention provides a timing controller including a transmitter for transmitting a transmission signal wherein a transmission clock signal is embedded therein between a transmission data signal to have a signal magnitude different from that of the transmission data signal. The present invention also provides a column driver integrated circuit including a receiving unit for separating a clock signal from a received signal using a magnitude of the received signal, and for performing a sampling of a received data signal from the received signal using the separated clock signal.
摘要（中）：

本发明涉及显示器，定时控制器和列驱动器IC，更具体地涉及使用时钟嵌入式多级信令的显示器，定时控制器和列驱动器集成电路。 本发明提供了一种定时控制器，其包括用于发送传输信号的发射机，其中传输时钟信号嵌入在传输数据信号之间，以具有与传输数据信号不同的信号幅度。 本发明还提供一种列驱动器集成电路，其包括接收单元，用于使用接收信号的幅度从接收信号中分离时钟信号，并且使用分离的时钟信号从接收信号中对接收到的数据信号进行采样 。

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