发明申请
US20080266965A1 NONVOLATILE SEMICONDUCTOR MEMORY HAVING PLURAL DATA STORAGE PORTIONS FOR A BIT LINE CONNECTED TO MEMORY CELLS
审中-公开
具有连接到存储单元的位线的多个数据存储部分的非易失性半导体存储器
- 专利标题： NONVOLATILE SEMICONDUCTOR MEMORY HAVING PLURAL DATA STORAGE PORTIONS FOR A BIT LINE CONNECTED TO MEMORY CELLS
- 专利标题（中）： 具有连接到存储单元的位线的多个数据存储部分的非易失性半导体存储器
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申请号： US12163676申请日： 2008-06-27
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公开(公告)号： US20080266965A1公开(公告)日： 2008-10-30
- 发明人: Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
- 申请人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 优先权： JP11-275327 19990928; JP11-345299 19991203
- 主分类号： G11C16/04
- IPC分类号： G11C16/04
摘要：
Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.
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