发明申请
US20080276032A1 ARRANGEMENTS WHICH WRITE SAME DATA AS DATA STORED IN A FIRST CACHE MEMORY MODULE, TO A SECOND CACHE MEMORY MODULE
审中-公开
将第一个高速缓存存储器模块中存储的数据写入数据的安排，第二个高速缓存存储器模块
- 专利标题： ARRANGEMENTS WHICH WRITE SAME DATA AS DATA STORED IN A FIRST CACHE MEMORY MODULE, TO A SECOND CACHE MEMORY MODULE
- 专利标题（中）： 将第一个高速缓存存储器模块中存储的数据写入数据的安排，第二个高速缓存存储器模块
-
申请号： US12132243申请日： 2008-06-03
-
公开(公告)号： US20080276032A1公开(公告)日： 2008-11-06
- 发明人: Junichi IIDA , Hiroki Kanai
- 申请人： Junichi IIDA , Hiroki Kanai
- 优先权： JP2004-249279 20040827
- 主分类号： G06F13/00
- IPC分类号： G06F13/00 ; H03M13/09
摘要：
A storage device control apparatus including first and second systematic memory module groups, each of which is composed of a plurality of memory modules, a memory controller for controlling memory access to the memory modules belonging to each of the first systematic and second systematic memory module groups. When the memory controller detects failure in one of the other memory systems, the memory system performs memory access to the memory modules belonging to its own systematic memory module groups.