发明申请
US20080277765A1 INHIBITING DAMAGE FROM DICING AND CHIP PACKAGING INTERACTION FAILURES IN BACK END OF LINE STRUCTURES
有权
从线路结构的后端引起的划线和芯片包装相互作用故障的损伤
- 专利标题: INHIBITING DAMAGE FROM DICING AND CHIP PACKAGING INTERACTION FAILURES IN BACK END OF LINE STRUCTURES
- 专利标题(中): 从线路结构的后端引起的划线和芯片包装相互作用故障的损伤
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申请号: US11746684申请日: 2007-05-10
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公开(公告)号: US20080277765A1公开(公告)日: 2008-11-13
- 发明人: Michael W. Lane , Xiao Hu Liu , Thomas M. Shaw , Mukta G. Farooq , Robert Hannon , Ian D. W. Melville
- 申请人: Michael W. Lane , Xiao Hu Liu , Thomas M. Shaw , Mukta G. Farooq , Robert Hannon , Ian D. W. Melville
- 申请人地址: US NY ARMONK
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY ARMONK
- 主分类号: H01L21/78
- IPC分类号: H01L21/78 ; H01L29/06
摘要:
A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.
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