发明申请
US20080286886A1 Monitoring Cool-Down Stress in a Flip Chip Process Using Monitor Solder Bump Structures
失效
使用显示器焊接凹凸结构监测倒装芯片工艺中的冷却应力
- 专利标题： Monitoring Cool-Down Stress in a Flip Chip Process Using Monitor Solder Bump Structures
- 专利标题（中）： 使用显示器焊接凹凸结构监测倒装芯片工艺中的冷却应力
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申请号： US11749885申请日： 2007-05-17
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公开(公告)号： US20080286886A1公开(公告)日： 2008-11-20
- 发明人: Charles F. Carey , Bernt Julius Hansen , Ashwani K. Malhotra , David L. Questad , Wolfgang Sauter
- 申请人： Charles F. Carey , Bernt Julius Hansen , Ashwani K. Malhotra , David L. Questad , Wolfgang Sauter
- 主分类号： H01L21/66
- IPC分类号： H01L21/66 ; H01L23/58
摘要：
A semiconductor chip and methods for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.