发明申请
US20080301599A1 METHOD FOR RAPID ESTIMATION OF LAYOUT-DEPENDENT THRESHOLD VOLTAGE VARIATION IN A MOSFET ARRAY
有权
MOSFET阵列快速估计依赖于阈值电压变化的方法
- 专利标题: METHOD FOR RAPID ESTIMATION OF LAYOUT-DEPENDENT THRESHOLD VOLTAGE VARIATION IN A MOSFET ARRAY
- 专利标题(中): MOSFET阵列快速估计依赖于阈值电压变化的方法
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申请号: US11757335申请日: 2007-06-01
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公开(公告)号: US20080301599A1公开(公告)日: 2008-12-04
- 发明人: Victor Moroz , Dipankar Pramanik
- 申请人: Victor Moroz , Dipankar Pramanik
- 申请人地址: US CA Mountain View
- 专利权人: SYNOPSYS, INC.
- 当前专利权人: SYNOPSYS, INC.
- 当前专利权人地址: US CA Mountain View
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations.
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