A pixel structure includes a gate, a source, a first drain, a second drain, a third drain, a first pixel electrode, a second pixel electrode, a scan line and a data line. The gate, the source and the first drain form a first thin film transistor. The gate, the source and the second drain form a second thin film transistor. The gate, the second drain and the third drain form a sub-thin film transistor (sub-TFT). Additionally, the first pixel electrode is electrically connected to the first drain, and the second drain extends to a portion between the second pixel electrode and the substrate such that a capacitor-coupling electrode is formed. Moreover, the second pixel electrode is electrically connected to the third drain of the sub-TFT. The scan line is disposed on the substrate and electrically connected to the gate, and the data line is electrically connected to the source.