发明申请
- 专利标题: Store Handling in a Processor
- 专利标题(中): 处理器中的商店处理
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申请号: US11758303申请日: 2007-06-05
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公开(公告)号: US20080307166A1公开(公告)日: 2008-12-11
- 发明人: Ramesh Gunna , Po-Yung Chang , Sudarshan Kadambi
- 申请人: Ramesh Gunna , Po-Yung Chang , Sudarshan Kadambi
- 主分类号: G06F12/00
- IPC分类号: G06F12/00
摘要:
In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load.
公开/授权文献
- US08239638B2 Store handling in a processor 公开/授权日:2012-08-07
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