An integrated circuit (IC) device fabrication process may be monitored by processing product wafers to fabricate product IC devices, collecting process tool data from tools used to fabricate the product IC devices, and testing the product IC devices. To predict and monitor yield, the process tool data collected during processing and the defectivity data from testing the product IC devices may be input to a yield model that also takes into account design information particular to the product devices. The design information may comprise layout attributes of the product devices. The yield model may be generated from a defectivity model created by processing test wafers to fabricate test structures, collecting process tool data from tools used to fabricate the test structures, and testing the test structures. The test structures may have varying layout attributes to cover a design space allowed by design rules for particular product IC devices.