A shift register circuit has a plurality of shift pulse generation circuits, and a scanning voltage generation circuit has a plurality of base circuits. The base circuits are presented with a first shift pulse generated by a shift pulse generation circuit, and a scanning line clock. The base circuits have a first transistor in which the first shift pulse is input to a first electrode, and a first power supply voltage is input to a control electrode; and a second transistor in which a control electrode is connected to a second electrode in the first transistor, a scanning line clock is input to the first electrode, and the second electrode is connected to a scanning voltage output terminal. The base circuits output a selected scanning voltage synchronized with the scanning line clock from the scanning voltage output terminal when the first shift pulse is at a first voltage level.