发明申请
- 专利标题: Techniques For Generating Bit Reliability Information In The Post Processor
- 专利标题(中): 在后处理器中生成位可靠性信息的技术
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申请号: US11771226申请日: 2007-06-29
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公开(公告)号: US20090006930A1公开(公告)日: 2009-01-01
- 发明人: Ivana Djurdjevic , Richard Leo Galbraith , Bruce Alexander Wilson , Yuan Xing Lee , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Zongwang Li
- 申请人: Ivana Djurdjevic , Richard Leo Galbraith , Bruce Alexander Wilson , Yuan Xing Lee , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Zongwang Li
- 申请人地址: NL Amsterdam
- 专利权人: Hitachi Global Storage Technologies Netherlands, B.V.
- 当前专利权人: Hitachi Global Storage Technologies Netherlands, B.V.
- 当前专利权人地址: NL Amsterdam
- 主分类号: H03M13/00
- IPC分类号: H03M13/00
摘要:
A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post processor selects a first most likely value from the first subset of the values and a second most likely value from the second subset of the values. The post processor generates a bit reliability based on the first and the second most likely values.
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