利索-全球专利检索

  1. 登录
  2. 注册
发明申请
US20090006931A1 Techniques For Generating Bit Reliability Information In A Post-Processor Using An Error Correction Constraint 有权
使用误差校正约束在后处理器中生成位可靠性信息的技术

Techniques For Generating Bit Reliability Information In A Post-Processor Using An Error Correction Constraint
摘要：
Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values.
摘要（中）：

提供了为检测到的序列生成位可靠性的技术。 检测器产生检测到的序列。 根据一个实施例，后处理器在检测到的序列中找到一个或多个错误事件的组合的第一组，其满足对应于第一位值的完整集合或纠错约束的子集，找到第二组组合 检测到的序列中的一个或多个错误事件满足对应于第二位值的完整集合或纠错约束的子集，选择第一集合中的一个或多个事件的第一最有可能的组合和第一集合的第二最有可能的组合 或更多的事件，并且基于第一和第二最有可能的值产生位可靠性。

公开/授权文献
信息查询
Global Dossier Espacenet
0/0