- 专利标题: Structure and manufactruing method of chip scale package
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申请号: US12206754申请日: 2008-09-09
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公开(公告)号: US20090011542A1公开(公告)日: 2009-01-08
- 发明人: Jin-Yuan Lee , Ching-Cheng Huang , Mou-Shiung Lin
- 申请人: Jin-Yuan Lee , Ching-Cheng Huang , Mou-Shiung Lin
- 申请人地址: TW Hsinchu
- 专利权人: MEGICA CORPORATION
- 当前专利权人: MEGICA CORPORATION
- 当前专利权人地址: TW Hsinchu
- 主分类号: H01L21/50
- IPC分类号: H01L21/50
摘要:
A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.
公开/授权文献
- US08748227B2 Method of fabricating chip package 公开/授权日:2014-06-10