发明申请
- 专利标题： DUAL WORD LINE OR FLOATING BIT LINE LOW POWER SRAM
- 专利标题（中）： 双字线或浮动位线低功率SRAM
-
申请号： US11775546申请日： 2007-07-10
-
公开(公告)号： US20090016122A1公开(公告)日： 2009-01-15
- 发明人: Shunsaku Tokito , Atsushi Hayashi
- 申请人： Shunsaku Tokito , Atsushi Hayashi
- 申请人地址： JP Tokyo
- 专利权人： SONY COMPUTER ENTERTAINMENT INC.
- 当前专利权人： SONY COMPUTER ENTERTAINMENT INC.
- 当前专利权人地址： JP Tokyo
- 主分类号： G11C7/00
- IPC分类号： G11C7/00 ; G11C29/00
摘要：
Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially dropping from a pre-charge level during operations in which a logic one is read from the anti-parallel storage circuit.
公开/授权文献
- US07545670B2 Dual word line or floating bit line low power SRAM 公开/授权日：2009-06-09
信息查询
