An amplifier stage or circuit for providing pre-emphasis. The circuit includes a first input node configured to receive a first data signal and a second input node configured to receive a second data. The circuit also includes an adjustable delay stage configured to at least partially produce a delay in the first and/or second data signals to thereby generate a first delayed signal and/or second delayed signal. The circuit additionally includes a pulse generation stage configured to generate a first pulse signal from the first delayed signal and the first data signal and/or produce a second pulse signal from the second delayed signal and the second data signal. The circuit further includes a first output node configured to output the first pulse signal and a second output node configured to output the second pulse signal.