Invention Application
- Patent Title: BLOCKING DIELECTRIC ENGINEERED CHARGE TRAPPING MEMORY CELL WITH HIGH SPEED ERASE
- Patent Title (中): 阻塞电路工程电荷捕捉存储单元高速擦除
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Application No.: US11845321Application Date: 2007-08-27
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Publication No.: US20090039416A1Publication Date: 2009-02-12
- Inventor: Sheng Chih Lai , Hang-Ting Lue , Chien Wei Liao
- Applicant: Sheng Chih Lai , Hang-Ting Lue , Chien Wei Liao
- Applicant Address: TW Hsinchu
- Assignee: Macronix International Co., Ltd.
- Current Assignee: Macronix International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L29/792
- IPC: H01L29/792 ; H01L21/336

Abstract:
A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.
Public/Granted literature
- US07737488B2 Blocking dielectric engineered charge trapping memory cell with high speed erase Public/Granted day:2010-06-15
Information query
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