发明申请
- 专利标题: INTEGRATED CIRCUIT PACKAGE AND MANUFACTURING METHOD THEREOF
- 专利标题(中): 集成电路封装及其制造方法
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申请号: US12201153申请日: 2008-08-29
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公开(公告)号: US20090057001A1公开(公告)日: 2009-03-05
- 发明人: Ji-Hyun JUNG , Shi-Yun Cho , Young-Min Lee , Youn-Ho Choi
- 申请人: Ji-Hyun JUNG , Shi-Yun Cho , Young-Min Lee , Youn-Ho Choi
- 优先权: KR2007-0088202 20070831
- 主分类号: H01R12/04
- IPC分类号: H01R12/04 ; H05K3/00
摘要:
An IC package includes: a multi-layered PCB having a plurality of insulating layers and a plurality of conductive pattern layers stacked in sequence and a plurality of via-holes formed through the plurality of the insulating layers for an electrical connection between the layers; and an IC chip disposed in a core insulating layer of the plurality of the insulating layers to be embedded in the multi-layered PCB and including a plurality of input/output pads on their surface. The input/output pads disposed at an outermost area of the IC chip are coupled to outer terminals by connection members without passing through said via-hole, the remaining input/output pads except for the input/output pads disposed at the outermost area of the IC chip are coupled to the outer terminals through the via-hole.
公开/授权文献
- US08053681B2 Integrated circuit package and manufacturing method thereof 公开/授权日:2011-11-08
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