发明申请
- 专利标题: SEMICONDUCTOR INTEGRATED CIRCUIT
- 专利标题(中): 半导体集成电路
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申请号: US11912272申请日: 2005-04-21
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公开(公告)号: US20090079465A1公开(公告)日: 2009-03-26
- 发明人: Toshio Sasaki , Yoshihiko Yasu , Ryo Mori , Koichiro Ishibashi , Yusuke Kanno
- 申请人: Toshio Sasaki , Yoshihiko Yasu , Ryo Mori , Koichiro Ishibashi , Yusuke Kanno
- 国际申请: PCT/JP2005/007596 WO 20050421
- 主分类号: H03K17/16
- IPC分类号: H03K17/16
摘要:
The present invention aims to make each power shutdown area appropriate.Cell areas each comprising a plurality of core cells arranged therein, and power switches disposed corresponding to the respective cell areas are provided. A plurality of power shutdown areas are respectively formed in units of the core cells. In each power shutdown area, power shutdown is enabled by the power switches corresponding to the power shutdown areas. Thus, the power shutdown areas can be set finely in the core cell units, and the appropriateness of each power shutdown area is achieved. With its appropriateness, a reduction in current consumption at standby is achieved.
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