The invention relates to an isolation trench structure and a corresponding layout wherein the insulating properties of isolation trenches (10, 10′) in critical areas (at intersections and junctions) are improved. Flattened and/or rounded off corner areas (10a, 10b) of the semiconductor regions to be insulated are produced, the etching and filling behavior being adjusted to be similar to that in the areas outside the critical areas, a center island (18, 18′) being provided for adapting the effective trench width in the critical areas of transition. The isolation trench structure is suitable for semiconductor arrangements (smart power applications) in which large voltage differences occur between the regions (12, 12′) to be electrically insulated from each other and the corresponding components. Power components can be integrated on the same chip together with small-signal elements.