Invention Application
- Patent Title: Wafer structure with a buffer layer
- Patent Title (中): 具有缓冲层的晶圆结构
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Application No.: US12285260Application Date: 2008-10-01
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Publication No.: US20090091036A1Publication Date: 2009-04-09
- Inventor: Chih-Hsing Chen , Tai-Yuan Huang
- Applicant: Chih-Hsing Chen , Tai-Yuan Huang
- Applicant Address: TW Kaohsiung
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW Kaohsiung
- Priority: TW96137179 20071003
- Main IPC: H01L23/532
- IPC: H01L23/532

Abstract:
A wafer structure with a buffer layer is provided. The wafer structure comprises a wafer which has at least one pad formed thereon, a passivation layer formed on the wafer for partially exposing the at least one pad, a buffer layer formed on the passivation layer and the pad, and an under bump metallurgy (UBM) formed on the buffer layer. The buffer layer comprises a thickness-increased inner buffering member made from aluminum and located between the UBM and the pad to enhance the shock-absorbing ability of the wafer in a drop test to avoid the conductive bump bonded to a substrate coming off or cracking. The invention can also enhance the bonding between the conductive bump and the UBM. The buffer layer may further comprise an outer buffering member made of polyimide, coated on the passivation layer and partially arranged between the UBM and the passivation layer.
Information query
IPC分类: