发明申请
- 专利标题: POWER SAVING DECODER ARCHITECTURE
- 专利标题(中): 节电解码器架构
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申请号: US11934394申请日: 2007-11-02
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公开(公告)号: US20090092184A1公开(公告)日: 2009-04-09
- 发明人: Hsi-Jung WU , Ionut HRISTODORESCU , Jim NORMILE
- 申请人: Hsi-Jung WU , Ionut HRISTODORESCU , Jim NORMILE
- 申请人地址: US CA Cupertino
- 专利权人: APPLE INC.
- 当前专利权人: APPLE INC.
- 当前专利权人地址: US CA Cupertino
- 主分类号: H04N11/02
- IPC分类号: H04N11/02
摘要:
A method and system are provided for decoding coded video data by turning off or not loading at least one functional unit or functional subunit of the decoder while decoding a portion of the coded video data. A schedule may be created prior to substantive decoding and then the schedule may be used to decode coded video data. The coded video data may be reordered based on the functional units or subunits the portions of the coded video data need for decoding. The portions of the coded video data are reordered into their original order in an output buffer after being decoded. The decoder may determine which functional units or subunits are needed for decoding based on administration information included with the coded video data. The decoder may decode portions of the coded video data in parallel.
公开/授权文献
- US08718129B2 Power saving decoder architecture 公开/授权日:2014-05-06