Invention Application
US20090097342A1 BUILT-IN SELF REPAIR CIRCUIT FOR A MULTI-PORT MEMORY AND METHOD THEREOF
失效
用于多端口存储器的内置自修复电路及其方法
- Patent Title: BUILT-IN SELF REPAIR CIRCUIT FOR A MULTI-PORT MEMORY AND METHOD THEREOF
- Patent Title (中): 用于多端口存储器的内置自修复电路及其方法
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Application No.: US11870169Application Date: 2007-10-10
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Publication No.: US20090097342A1Publication Date: 2009-04-16
- Inventor: Tsu-Wei Tseng , Yu-Jen Huang , Chun-Hsien Wu , Jin-Fu Li , Chien-Yuan Pao
- Applicant: Tsu-Wei Tseng , Yu-Jen Huang , Chun-Hsien Wu , Jin-Fu Li , Chien-Yuan Pao
- Applicant Address: TW Hsinchu
- Assignee: FARADAY TECHNOLOGY CORP.
- Current Assignee: FARADAY TECHNOLOGY CORP.
- Current Assignee Address: TW Hsinchu
- Main IPC: G11C29/12
- IPC: G11C29/12

Abstract:
A built-in self repair (BISR) circuit for a multi-port memory and a method thereof are provided. The circuit includes a test-and-analysis module (TAM) and a defect locating module (DLM) coupled to the TAM. The TAM tests a repairable multi-port memory to generate a fault location and determines whether the test generates a port-specific fault candidate according to the fault location. If a port-specific fault candidate is generated, the DLM generates a defect location based on the fault location and provides the defect location to the TAM so that the TAM can determine how to repair the repairable multi-port memory according to the defect location. If no port-specific fault candidate is generated in the test, the TAM determines how to repair the repairable multi-port memory according to the fault location.
Public/Granted literature
- US07596728B2 Built-in self repair circuit for a multi-port memory and method thereof Public/Granted day:2009-09-29
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