发明申请
- 专利标题: METHOD OF FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE
- 专利标题(中): 在半导体器件中形成隔离层的方法
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申请号: US12163328申请日: 2008-06-27
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公开(公告)号: US20090098740A1公开(公告)日: 2009-04-16
- 发明人: Jung Geun Kim , Cheol Mo Jeong , Whee Won Cho
- 申请人: Jung Geun Kim , Cheol Mo Jeong , Whee Won Cho
- 申请人地址: KR Icheon-si
- 专利权人: HYNIX SEMICONDUCTOR INC.
- 当前专利权人: HYNIX SEMICONDUCTOR INC.
- 当前专利权人地址: KR Icheon-si
- 优先权: KRKR10-2007-0102159 20071010
- 主分类号: H01L21/31
- IPC分类号: H01L21/31 ; H01L21/469
摘要:
The invention discloses a method of forming an isolation layer in a semiconductor device. The method includes providing a semiconductor substrate having a trench formed therein; forming a first insulating layer in the trench; and forming a densified second insulating layer on the first insulating layer. In the above method, a void is not generated in the isolation layer so a bending phenomenon of an active region can be reduced or prevented to improve an electrical characteristic of the semiconductor.
公开/授权文献
- US07892919B2 Method of forming isolation layer in semiconductor device 公开/授权日:2011-02-22
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