发明申请
US20090119456A1 PROCESSOR AND MEMORY CONTROL METHOD 有权
处理器和存储器控制方法

PROCESSOR AND MEMORY CONTROL METHOD
摘要:
A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports.
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