Invention Application
- Patent Title: SYSTEM AND METHOD FOR GENERATING ERROR TRACES FOR CONCURRENCY BUGS
- Patent Title (中): 用于产生差错误差的系统和方法
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Application No.: US12241340Application Date: 2008-09-30
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Publication No.: US20090125887A1Publication Date: 2009-05-14
- Inventor: Vineet Kahlon , Sriram Sankarnarayanan , Aarti Gupta
- Applicant: Vineet Kahlon , Sriram Sankarnarayanan , Aarti Gupta
- Applicant Address: US NJ Princeton
- Assignee: NEC LABORATORIES AMERICA, INC.
- Current Assignee: NEC LABORATORIES AMERICA, INC.
- Current Assignee Address: US NJ Princeton
- Main IPC: G06F9/44
- IPC: G06F9/44

Abstract:
A system and method for program verification includes generating a product transaction graph for a concurrent program, which captures warnings for potential errors. The warnings are filtered to remove bogus warnings, by using constraints from synchronization primitives and invariants that are derived by performing one or more dataflow analysis methods for concurrent programs. The dataflow analysis methods are applied in order of overhead expense. Concrete execution traces are generated for remaining warnings using model checking.
Public/Granted literature
- US08527976B2 System and method for generating error traces for concurrency bugs Public/Granted day:2013-09-03
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