发明申请
- 专利标题: SYSTEM AND METHOD FOR GENERATING ERROR TRACES FOR CONCURRENCY BUGS
- 专利标题(中): 用于产生差错误差的系统和方法
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申请号: US12241340申请日: 2008-09-30
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公开(公告)号: US20090125887A1公开(公告)日: 2009-05-14
- 发明人: Vineet Kahlon , Sriram Sankarnarayanan , Aarti Gupta
- 申请人: Vineet Kahlon , Sriram Sankarnarayanan , Aarti Gupta
- 申请人地址: US NJ Princeton
- 专利权人: NEC LABORATORIES AMERICA, INC.
- 当前专利权人: NEC LABORATORIES AMERICA, INC.
- 当前专利权人地址: US NJ Princeton
- 主分类号: G06F9/44
- IPC分类号: G06F9/44
摘要:
A system and method for program verification includes generating a product transaction graph for a concurrent program, which captures warnings for potential errors. The warnings are filtered to remove bogus warnings, by using constraints from synchronization primitives and invariants that are derived by performing one or more dataflow analysis methods for concurrent programs. The dataflow analysis methods are applied in order of overhead expense. Concrete execution traces are generated for remaining warnings using model checking.
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